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analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems features adc and dac: ? 100 db dynamic range ? ?90 db thd ? 8 khz to 200 khz sampling frequency ? i 2 s, left justified and right ju stified audio data format, 16- 24 bits ? 128, 192, 256, 384, 512, 768 and 1024 mclk to lrck ratios ? independent adc and dac sampling frequencies and clocks ? advanced multi-bit delta-sigma with low sensitivity to clock jitter ? single power supply from 3v to 5.5v ? hardware mode or spi or 2-wire uc interface adc: ? 4-to-1 mux for analog inputs ? direct 2 v rms analog input ? adc pga from 11.5 db to ?11.5 db in 0.5 db per step ? digital attenuation from 6.5 db to 89.5 db in 0.5 db per step ? optional high pass filter to remove analog dc offset dac: ? digital volume control from 0 db to 120 db attenuation in 0.5 db per step, with soft ramp and zero crossing transition ? de-emphasis filter for 32, 44.1 and 48 khz sampling frequencies ? selectable fast and slow roll-off filters ? 95 db dynamic range ? -85 db thd+n ? up to 200 khz sampling frequency ? i 2 s audio data format, 16-24 bits ? single power supply 4.5 v to 5.5v applications ? dvd recorder ? personal video recorder ? lcd and digital tvs ? car audio ? av receiver general description PA5322 is a low cost high perf ormance stereo audio codec. PA5322 performs stereo digital to analog conversion and analog to digital conversion continuously from 8 khz to 200 khz sampling frequency. PA5322 is ideal for high performance cost sensitive c onsumer audio applications. PA5322 can accept i2s; left justif ied and right justified serial audio data formats up to 24-bit word length. adc and dac operate on independent sampling frequencies and clocks. the device uses advanced multi-bit ( ? -) delta-sigma modulation technique to convert data between digital and analog. the multi-bit ( ? - ) delta-sigma modulators makes the device with low sensitivity to clock jitter and low out of band noise. PA5322 can operate either in the hardware mod or the software mode. in the hardware mode, pin m0, m1, m2 and m3 set the operation of the device. in the software mode, PA5322 provides spi or 2-wire micro-controller interfaces to configure its operations. block diagram ordering information temperature range package part number -40 to 85 c ssop-28 PA5322-t7 95248 a dclrck a dcsclk a dcsdout /m3 a dcmclk adc clock manage r input mux/mix pga a dc serial port c interface dac clock manage r dsp output amp low pass filte r multilevel sigma delta dac dac serial port dacmclk a in3l/r a in4l/r a in2l/r 5k ? a in1l/r d a clrck dacsclk dacsdin a outl a outr 5k ? multilevel sigma delta adc dsp cdata/m1 cclk/m2 ce/mo
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems pin configuration pin descriptions pin pin no. pin description adc pin. a in1l/r 20, 19 analog input 1 left and right channels a in2l/r 23, 18 analog input 2 left and right channels a in3l/r 24, 17 analog input 3 left and right channels a in4l/r 25, 16 analog input 4 left and right channels adcmclk 9 adc master clock adcsdout/m3 10 adc pcm serial data output adclrck 5 adc pcm serial data left and right channel frame clock adcsclk 6 adc pcm serial data bit clock dacmclk 4 dac master clock dacsdin 1 dac pcm serial data input daclrck 2 dac pcm serial data left and right channel frame clock dacsclk 3 dac pcm serial data bit clock aoutl/r 28, 27 dac analog output left and right channels mute 14 mute pin, active when detect 8k zero input in both left and right channels or users choose to mute the dac dac pin. ce/m0 13 spi uc interface chip select or 2-wire ad0 cclk/m2 11 spi or 2-wire (i2c compatible) uc interface clock cdata/m1 12 spi or 2-wire (i2c compatible) uc interface data micro-controller pin or hardware mode pin. v ddd /gnd d 7, 8 digital power supply v dda /gnd a 22, 21 analog power supply adc refp /dac refp 15, 26 analog filtering pins a in4l a outl vdda dacrefp a outr gnda a dcrefp a in4r a in2l a in3l a in1r a in1l a in3r a in2r adcmcl k adclrc k vddd adcsdout/m3 daclrc k adcscl k gndd dacsdin mute dacscl k ce/m0 cdata/m1 cclk/m2 dacmcl k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems in hardware mode, the mode pins function as follows: pin pin no. pin description m3 10 external pull-up (47k resistor) ? adc and dac i 2 s serial data format external pull-down (47k resistor) ? adc and dac lj serial data format m2 11 0 ? no de-emphasis 1 ? 44.1 khz de-emphasis filter on m1:m0 12, 13 00 ? select ain1 01 ? select ain2 10 ? select ain3 11 ? select ain4 absolute maximum ratings supply voltage ??????????. min-0.3v max +7.0v input voltage ??????? min gnd-0.3v max v dd +0.3v operating temperature??????..min -40c max +85c storage temperature???????min -65c max +150c note: continuous operation at or beyond these conditions may permanently damage the device. recommended operating conditions analog supply vo ltage ??????? min 3.0v max 5.5v digital supply voltage ??????? min 3.0v max 5.5v adc analog and filter characteristics and specifications test conditions are as the following unless otherwise specify: vdda=+5.0v, vddd=+5.0v, gnda=0v, gndd=0v, ambient temperature=+25 ? c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. parameter min typ max unit adc performance dynamic range (note 1) 85 95 100 db thd+n -90 -86 -80 db channel separation (1khz) 80 85 90 db signal to noise ratio 85 95 100 db inter-channel gain mismatch 0.1 db gain error 5 % filter frequency response ? single speed pass-band 0 0.4535 fs stop-band 0.5465 fs pass-band ripple 0.05 db stop-band attenuation 70 db filter frequency response ? double speed pass-band 0 0.4167 fs stop-band 0.5833 fs pass-band ripple 0.005 db stop-band attenuation 70 db filter frequency response ? quad speed pass-band 0 0.2083 fs stop-band 0.7917 fs pass-band ripple 0.005 db
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems stop-band attenuation 70 db analog input full scale input level (note 2) 2*(vdda/5) vrms input impedance 10 k ? note 1. the value is measured used a-weighted filter . if not use, the result will decrease 2-3 db. 2. PA5322 allows direct 2 v rms inputs if external 5 k ? resistors are used in serial with the analog input pins. 1 v rms inputs can directly apply to the analog input pins. dac analog and filter characteristics and specifications test conditions are as the following unless otherwise specify: vdda=+5.0v, vddd=+5.0v, gnda=0v, gndd=0v, ambient temperature=+25 ? c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. parameter min typ max unit dac performance dynamic range (note 1) 85 98 100 db thd+n -90 -82 -75 db channel separation (1khz) 80 85 90 db signal to noise ratio 85 97 100 db inter-channel gain mismatch 0.05 db filter frequency response ? single speed, fast roll-off filter pass-band 0 0.4535 fs stop-band 0.5465 fs pass-band ripple 0.05 db stop-band attenuation 53 db filter frequency response ? double speed, fast roll-off filter pass-band 0 0.4167 fs stop-band 0.5833 fs pass-band ripple 0.005 db stop-band attenuation 56 db filter frequency response ? quad speed, fast roll-off filter pass-band 0 0.2083 fs stop-band 0.7917 fs pass-band ripple 0.006 db stop-band attenuation 50 db filter frequency response ? single speed, slow roll-off filter pass-band 0 0.4167 fs stop-band 0.5833 fs pass-band ripple 0.05 db stop-band attenuation 65 db filter frequency response ? double speed, slow roll-off filter pass-band 0 0.2083 fs stop-band 0.7917 fs pass-band ripple 0.005 db stop-band attenuation 85 db filter frequency response ? quad speed, slow roll-off filter
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems pass-band 0 0.1042 fs stop-band 0.8958 fs pass-band ripple 0.005 db stop-band attenuation 55 db de-emphasis error at 1 khz (single speed mode only) fs = 32khz fs = 44.1khz fs = 48khz 0.002 0.013 0.0009 db analog output full scale output level 0.7*vdda vpp output impedance 120 ? load resistance 2 k ? load capacitance 100 pf note 1. the value is measured used a-weighted filter. dc characteristics and specifications parameter min typ max unit normal operation mode v ddd =v dda =5.0v: v ddd current v dda current v ddd =v dda =3.3v: v ddd current v dda current 42 55 34 50 ma power down mode v ddd =v dda =5.0v: v ddd current v dda current v ddd =v dda =3.3v: v ddd current v dda current tbd tbd tbd tbd ma digital voltage level input high-level voltage 2.0 v input low-level voltage 0.8 v output high-level voltage vddd v output low-level voltage 0 v mute pin drive capability 3.0 ma serial audio port swit ching specifications parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low t sclkl 15 ns sclk pulse width high t sclkh 15 ns
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems sclk falling to lrck edge t slr ?10 10 ns sclk falling to sdout valid t sdo 0 ns sdin valid to sclk rising setup time t sdis 10 ns sclk rising to sdin hold time t sdih 10 ns serial audio port timing serial control port sw itching specifications parameter symbol min max unit spi mode spi_clk clock frequency 10 mhz spi_clk edge to spi_csn falling t spics 5 ns spi_csn high time between transmissions t spish 500 ns spi_csn falling to spi_clk edge t spisc 10 ns spi_clk low time t spicl 45 ns spi_clk high time t spich 45 ns spi_din to spi_clk rising setup time t spids 10 ns spi_clk rising to data hold time t spidh 15 ns 2-wire mode scl clock frequency f scl 100 khz bus free time between transmissions t twid 4.7 us start condition hold time t twsth 4.0 us clock low time t twcl 4.0 us clock high time t twch 4.0 us setup time for repeated start condition t twsts 4.7 us sda hold time from scl falling t twdh 0.1 us sda setup time to scl rising t twds 100 ns rise time of scl t twr 25 us fall time scl t twf 25 ns lrc k input slc k input sdout sdin t slr t sdo t sclkh t sclkw t sdis t sdih t sclkl
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems 5 k ? 5 k ? 5 k ? 5 k ? 5 k ? 5 k ? 5 k ? 5 k ? v ddd 0.1 f 10 f 47 h 7 7 8 v ddd gnd d 1 2 3 4 5 6 9 10 11 12 13 14 mute ce cdata cclk adcsout adcmclk adcsclk adclrck dacmclk dacsclk daclrck dacsdin dac serial audio data adc serial audio data mcu interface external mute circuit a outl a out r dacrefp ain4l ain3l ain2l ain1l ain1r ain2r ain3r ain4r adcrefp gnd a v dd a 15 16 17 18 19 21 22 20 23 24 25 26 27 28 analog right inputs analog left inputs 0.1 f 10 f 47 h 4.7 f 4.7 f 4.7 f 4.7 f v dda 0.1 f 10 f 4.7 f 4.7 f 4.7 f 4.7 f 0.1 f 10 f v out l/r to external lpe spi_din spi_clk spi_csn t spics t spisc t spids t spidh t spich t spicl t spish serial control port spi timing s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid serial control port 2-wire timing recommended application circuit
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems audio data sampling frequency and clocks according to the input serial audio data sampling frequency, t he device can work in three speed modes: single speed, double spe ed or quad speed modes. the ranges of the sampling frequen cy in these three modes are listed in table1. adcsamplerate bits in adc control 2 register (ram address 0x 02) or dacsamplerate bits in dac control 2 register (ram address 0x07) set the speed mode. by default, the device can detect the speed mode automatically wh en sampling rate falls within the fs auto detection ranges lis ted in table1. in this auto detection mode, sampling frequency outside the spec ified ranges is not supported. adc and dac have separate auto detection so adc and dac sampling frequencies can be completely independent. table 1. sampling frequency and clk/lrck ration speed mode sampling frequency fs auto detection range mclk/lrck ratio single speed 8khz ? 50khz 8khz ? 50khz 256, 384, 512, 768, 1024 double speed 50khz ? 100khz 84khz ? 100khz 128, 192, 256, 384, 512 quad speed 100khz ? 200khz 167khz ? 200khz 128, 192, 256 the device uses separate master clocks, lrck clocks and sclk clocks for the adc and dac. the allowed mclk/lrck ratios in each speed mode are also listed in table1. the devic e always detects mclk/lrck ratio automatically. hardware mode the device can operate in the hardware mode or the software mode. the default is the hardwar e mode. to change the hardware mode to the software mode, set scpen bit of chip control register (ram address 0x00) to 1. in the hardware mode, pin m3 sets i 2 s or left justified adc and dac serial port mode, pin m2 sets dac de-emphasis filter on or off, and pins m1 and pin m0 select one of the four adc analog inputs. please refer to pin description s section for detail settings. power up and down the chip internal power on reset will reset the device when vddd ramps from ground to supply voltage level. when vddd and vdda are present to the device, applying adcmclk and adclrck will startup the adc and applying dacmclk and daclrck will start up the dac. during the dac startup, dac analog outputs ramp gradually from ground to mid level to minimize audible pop noise. this gradual ramp feature can be turned off by setting clickfree bit of dac control 1 register (ram address 0x06) to 0. adc and dac can power up or down independently. in the soft ware mode, adc or dac can power down through adcpdn bit or dacpdn bit of chip control register (ram address 0x00). in the hardware mode, adc can power down by stopping adcmclk or adclrck, and dac can power down by stopping dacmclk or daclrck. micro-controller configuration interface the device supports standard spi and 2-wire mi cro-controller configuration interface. external micro-controller can completely configure the device through writing to internal configuration registers. the identical device pins are used to configure either spi or 2-wire interface. in spi mode, pin ce, cclk and cdata function as spi_csn, spi_clk and spi_din. in 2-wire mode, pin ce , cclk and cdata function as ad0, scl and sda. to select spi mode, apply high to low transition signal to ce pin. otherwise the device will oper ate in 2-wire interface mode. spi PA5322 has a spi (serial peripheral interface) compliant synchronous serial slave controller inside the chip. it provides the a bility to allow the external master spi controller to access the inte rnal registers, and thus co ntrol the operations of chip. all lines on the spi bus are unidirectional: the spi_clk is gener ated by the master controller and is primarily used to synchro nize data transfer, the spi_din line carries data from the master to the slave; spi_csn is generated by the master to select PA5322. the timing diagram of this interface is given in figure 1. the high to low transition at spi_csn pin indicates the spi interfac e selected. each write procedure contains 3 wo rds, i.e. chip address plus r/w bit, inte rnal register address and internal registe r data. every word length is fixed at 8 bits. the input spi_din data are sampled at the rising edge of spi_clk clock. the msb bit in ea ch word is transferred firstly. the transfer rate can be up to 10m bps.
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems chip address 7 bits - 0010000 0 spi_din spi_clk spi_csn 1 r/ wb 567 8 9141516 17 22 23 ram 8 bits register data 8 bits ram = register address mapping figure1. spi configuration interface timing diagram 2-wire 2-wire interface is a bi-directional serial bus that uses a se rial data line (sda) and a serial clock line (scl) for data trans fer. the timing diagram for data transfer of this interface is given in fi gure 2. data are transmitted synchronously to scl clock on the sda line on a byte-by-byte basis. each bit in a byte is sampled during scl high with msb bit being transmitted firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the sda low. the transfer rate of this interface can be up to 100k bps. 1-7 8 9 1-7 8 9 1-7 8 s p sda scl start address r/w ack data ack data stop figure2. complete data transfer 2-wire interface a master controller initiates the transmission by sending a ?sta rt? signal, which is defined as a high-to-low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven-bit chip address followed by a rw bit. the chip address must be 001000x, where x equals ad0 (pin ce). the rw bit indicates the slave data transfer direction. once an acknowledge bit is receiv ed, the data transfer starts to proceed on a byte-by-byte basis in t he direction specified by the rw bit. the master can terminate the communication by generating a ?stop? signal, which is defin ed as a low-to-high transition at sda while scl is high. in 2-wire interface mode, the registers can be written and read. the formats of ?write? and ?read? instructions are shown in ta ble 2 and table 3. please note that, to read data from a register, you must set r/w bit to 0 to access the register address and then set r/w to 1 to read data from the register. there are no acknowledge bi t after data to be written or read, this is the only difference from the i 2 c protocol. table 2 write data to register in 2-wire interface mode chip address r/w regist er address data to be written 001000 ad0 0 ack ram ack data table 3 read data from register in 2-wire interface mode chip address r/w register address 001000 ad0 0 ack ram chip address r/w data to be read 001000 ad0 1 ack data
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems configuration register definition spi and 2-wire configuration interface share the same registers because there is only one interface active at any time. there a re total of 11 user programmable 8-bit registers in this device. these registers control the operat ions of adc and dac. external master controll er can access these registers by using the slave address specified in ram (register address map) register as shown in table 2. table 2 bit content of register address map bit name bit description ram address 7:0 the address of the register to be accessed: 0x00 ? chip control (default) 0x01 ? adc control 1 0x02 ? adc control 2 0x03 ? adc mute control 0x04 ? adc left gain control 0x05 ? adc right gain control 0x06 ? dac control 1 0x07 ? dac control 2 0x08 ? dac mute control 0x09 ? dac left volume control 0x0a ? dac right volume control chip control ? 0x00 bit name bit description scpen 7 0 ? hardware mode (default) 1 ? software (control port) mode reserved 6:5 reserved adcpdn 4 0 ? normal (default) 1 ? adc low power mode reserved 3 reserved dacpdn 2 0 ? normal (default) 1 ? dac low power mode reserved 1:0 reserved adc control 1 ? 0x01 bit name bit description ainmix 7:3 00000 ? ain1 input to adc (default) xxx1 ? ain1 input adc xx1x ? ain2 input adc x1xx ? ain3 input adc 1xxx ? ain4 input adc hpf 2 0 ? adc hpf enable (default) 1 ? adc hpf disable reserved 1:0 reserved adc control 2 ? 0x02 bit name bit description adcsamplerate 7:6 00 ? adc speed mode auto detect (default) 01 ?single speed mode 10 ?double speed mode 11 ?quad speed mode adcspdatamode 5:3 000 ? left just ified, up to 24 bit data
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems 001 ? i 2 s, up to 24 bit data (default) 010 ? right justified, 16 bit data 011 ? reserved 100 ? reserved 101 ? right justified, 24 bit data 110 ? reserved 111 ? reserved sclkratio 2:1 00 ? 32 01 ? 48 10 ? 64 (default) 11 ? 128 reserved 0 reserved adc mute control ? 0x03 bit name bit description adcmute 7 0 ? normal (default) 1 ? mute adc digital output reserved 6 reserved adcramprate 5:4 these bits define adc gain control ramp rate: 00 ? 0.5 db per 4 lrck (default) 01 ? 0.5 db per 8 lrck 10 ? 0.5 db per 16 lrck 11 ? 0.5 db per 32 lrck adcl=r 3 0 ? normal (default) 1 ? both channel gain control is set by adc left gain control register adcsoftramp 2 adc soft ramp at mute or gain change: 0 ? disabled 1 ? enabled (default) adczerocrs 1 adc mute or gain change at zero crossing signal level to minimize audible noise 0 ? disabled 1 ? enabled (default) reserved 0 reserved adc left gain control ? 0x04 bit name bit description adcgainl 7:0 1110 1000 ? 6.0 db gain (pga) 1110 1001 ? 6.5 db gain (pga) 1110 1010 ? 7.0 db gain (pga) 1110 1011 ? 7.5 db gain (pga) 1110 1100 ? 8.0 db gain (pga) 1110 1101 ? 8.5 db gain (pga) 1110 1110 ? 9.0 db gain (pga) 1110 1111 ? 9.5 db gain (pga) 1111 0000 ? 10.0 db gain (pga) 1111 0001 ? 10.5 db gain (pga) 1111 0010 ? 11.0 db gain (pga) 1111 0011 ? 11.5 db gain (pga) 1111 0100 ? 6.0 db attenuation (pga) 1111 0101 ? 5.5 db attenuation (pga) 1111 0110 ? 5.0 db attenuation (pga) 1111 0111 ? 4.5 db attenuation (pga) 1111 1000 ? 4.0 db attenuation (pga) 1111 1001 ? 3.5 db attenuation (pga) 1111 1010 ? 3.0 db attenuation (pga)
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems 1111 1011 ? 2.5 db attenuation (pga) 1111 1100 ? 2.0 db attenuation (pga) 1111 1101 ? 1.5 db attenuation (pga) 1111 1110 ? 1.0 db attenuation (pga) 1111 1111 ? 0.5 db attenuation (pga) 0000 0000 ? no gain or attenuation (default) 0000 0001 ? 0.5 db gain (pga) 0000 0010 ? 1.0 db gain (pga) 0000 0011 ? 1.5 db gain (pga) 0000 0100 ? 2.0 db gain (pga) 0000 0101 ? 2.5 db gain (pga) 0000 0110 ? 3.0 db gain (pga) 0000 0111 ? 3.5 db gain (pga) 0000 1000 ? 4.0 db gain (pga) 0000 1001 ? 4.5 db gain (pga) 0000 1010 ? 5.0 db gain (pga) 0000 1011 ? 5.5 db gain (pga) 0000 1100 ? 6.0 db gain (pga) 0000 1101 ? 11.5 db attenuation (pga) 0000 1110 ? 11.0 db attenuation (pga) 0000 1111 ? 10.5 db attenuation (pga) 0001 0000 ? 10.0 db attenuation (pga) 0001 0001 ? 9.5 db attenuation (pga) 0001 0010 ? 9.0 db attenuation (pga) 0001 0011 ? 8.5 db attenuation (pga) 0001 0100 ? 8.0 db attenuation (pga) 0001 0101 ? 7.5 db attenuation (pga) 0001 0110 ? 7.0 db attenuation (pga) 0001 0111 ? 6.5 db attenuation (pga) 0001 1000 ? 6.0 db attenuation (pga) 0001 1001 ? 6.5 db attenuation (6 db pga + digital attenuation) 0001 1010 ? 7.0 db attenuation (6 db pga + digital attenuation) ??.. 1011 1111 ? 89.5 db attenuation (6 db pga + digital attenuation) adc right gain control ? 0x05 bit name bit description adcgainr 7:0 same as adcgainl settings for adc right channel dac control 1 ? 0x06 bit name bit description reserved 7:6 reserved clickfree 5 0 ? disable pop noise suppression power up and down 1 ? enable pop noise suppression power up and down (default) slowfilter 4 0 ? fast filter roll off (default) 1 ? slow filter roll off invl invr 3:2 0 ? dac analog output no phase inversion (default) 1 ? dac analog output 180 degree phase inversion reserved 1:0 reserved dac control 2 ? 0x07 bit name bit description dacsamplerate 7:6 00 ? dac speed mode auto detect (default) 01 ? single speed mode 10 ? double speed mode 11 ? quad speed mode dacspdatamode 5:3 000 ? left justified, up to 24 bit data
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems 001 ? i 2 s, up to 24 bit data (default) 010 ? right justified, 16 bit data 011 ? reserved 100 ? reserved 101 ? right justified, 24 bit data 110 ? reserved 111 ? reserved deemphasismode 2:1 00 ? de-empha sis filter disabled (default) 01 ? de-emphasis filter for fs=32 khz 10 ? de-emphasis filter for fs=44.1 khz 11 ? de-emphasis filter for fs=48 khz reserved 0 reserved dac mute control ? 0x08 bit name bit description dacmute 7 0 ? un-mute analog outpu ts for both channels (default) 1 ? mute analog outputs for both channels dacramprate 6 these bits define volume control ramp rate: 00 ? 0.5 db per 4 lrck (default) 01 ? 0.5 db per 8 lrck 10 ? 0.5 db per 16 lrck 11 ? 0.5 db per 32 lrck automute 5 auto mute function: long period of zero inputs (8k audio samples) will mute the analog output. any single non-zero input will un-mute. 0 ? disable 1 ? enable (default) dacl=r 4 0 ? normal (default) 1 ? both channel volume control is set by left volume control register dacsoftramp 3 soft ramp at mute and volume change: 0 ? disabled 1 ? enabled (default) daczerocrs 1 mute or volume change at zero cr ossing signal level to minimize audible noise 0 ? disabled 1 ? enabled (default) reserved 0 reserved dac left volume control ? 0x09 bit name bit description dacvolumel 7:0 digital volume control setting attenuates the signal in 0.5 db incremental from 0 to ?120 db. max setting is ?120 db. 0000 0000 ? no attenuation (default) 0000 0001 ? 0.5 db attenuation 0000 0010 ? 1.0 db attenuation 0000 0011 ? 1.5 db attenuation ??.. dac right volume control ? 0x0a bit name bit description dacvolumer 7:0 same as dacvolumel settings for dac right channel digital audio interface the device provides three formats of serial audio data interface to the input of the dac or output from the adc through lrck, s clk and sdin/sdout pins. the three formats are i 2 s, left justified and right justified. in t he hardware mode, the formats are selected through pin m3.
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems in the software mode, the formats are selected by adcspdatam ode bits of adc control 2 register (ram address 0x02) or dacspdatamode bits dac control 2 register (ram address 0x07). dacsdin is sampled by PA5322 on the rising edge of dacsclk. adc data is out on adcsdout and changes on t he falling edge of adcsclk. the relationship of sdata (sdin/sdout), sclk and lrck with the three formats is shown below through figure 3 to figure 5. n- 2 n- 1 n 3 2 1 1 sclk msb lsb left channel n- 2 n- 1 n 3 2 1 1 sclk msb lsb right channel sdata sclk lrck figure 3. i 2 s audio data format up to 24-bit n- 2 n- 1 n 3 2 1 msb lsb left channel n- 2 n- 1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 4. left justified audio data format up to 24-bit n- 2 n- 1 n 3 2 1 msb lsb left channel n- 2 n- 1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 5. right justified audio data format up to 24-bit analog input multiplex and programmable gain control PA5322 allows direct 2 v rms inputs if external 5 k ? resistors are used in serial with the analog input pins. please refer to figure 6. v rms inputs can directly apply to the analog input pins. in the hardware mode, the analog input is selected through mode pins m1 and m0. in the software mode, the analog input is selec ted through ainmix bits of adc control 1 register (ram address 0x01) . in the software mode, more than one input can apply to the analog input pins to achieve mixing effects. figure 6. adc left and right inputs the adc has an analogue input pga and digital gain control for eac h stereo channel. the analog pga has a range of +12 db to ?12 db gains in 0.5 db per step. the digital gain control allows furt her attenuation (after the pga) fr om 12.5 db to 96 db in 0.5 d b per step. adc left gain control register (ram address 0x04) and adc right gain control register (ram address 0x05) allows independent control of left and right channel gains. 5k 5k 5k 5k 5k 5k 5k 5k 5k opamp +12 db to ?12 db pga PA5322 a in1l/r a in2l/r a in3l/r a in4l/r
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems zero crossing detection and soft ramp control circuits are prov ided for the adc gain control (adc mute control register, ram ad dress 0x03). this feature minimizes the audible click and ?zipper? noise as the gain values change. dac fade in and fade out transition when dacmute bit in dac mute control register (ram address 0x 08) is set, the analog outputs go to mute level (common mode voltage) gradually at the rate set by dacramprate bits in t he same register. upon the releas e of the dacmute bit, the analog outputs go up gradually at the same rate set by dacramprate bits. please refer to figure 7. the fade in and fade out feature can be set or disa bled by dacsoftramp bit in the same register. mute bit volume level aout figure 7. fade in/out diagram the fade in and fade out feature is also available when automute bit in dac mute control register (ram address 0x08) is set to detect long stream of zero input data.
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems package dimensions and measurements 28-pin ssop outline dimensions
analog products division 561 e. elliot road #175 chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715 www.protekanalog.com PA5322 100db, 24-bit, 192 khz stereo audio codec 95248 rev.0. 01/10 not for use in life support systems life support policy protek analog's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of protek devices.

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